Present commercial photolithography, more particularly photolithography for use in semiconductor processing, uses light to expose a substrate coated with a photosensitive material (also known as a "resist" coating) through a mask. The mask has an opaque pattern that blocks some of the light. The "resist" material that is sufficiently exposed to the light not blocked by the mask acquires a characteristic that is different from the resist that is blocked by the mask from the light. As a result, the exposed resist can be "developed," that is physically removed by a chemical processing to expose the substrate. The substrate is then processed by a semiconductor processing step, e.g., doping the exposed substrate with an "n" or a "p" material, or oxidizing the exposed substrate, it being understood that other processing treatments could be applied in a conventional manner. The portion of the substrate that remains coated by resist remains comparatively unaffected by this further processing. Then, the so-processed substrate is further processed to remove the remainder of the resist coating, leaving the substrate having an n, p, or oxidized material formed therein in the pattern of the mask. Thereafter, another resist coating may be applied, a different mask used to expose the resist and a different pattern of n or p material, or oxidation is formed in the substrate to form a different layer of material. By this technique of repeated photolithographic exposure through a mask and processing, the semiconductor material is formed into an integrated circuit (more specifically a plurality of integrated circuits) as is well known. Although the present invention is by no means limited to semiconductor processing to form integrated circuits, such techniques provide a useful framework for understanding the invention, as discussed below.
Current photolithography has a resolution with dimensions on the micrometer level. Stated otherwise, the smallest dimension of a line (such as a wire or lead connecting two circuit elements) that can be made using photolithography is approximately 0.2 micrometers. This dimensional limit controls the size of the circuit elements used in the semiconductor chip, and thus how many circuits can be formed in a given amount of real estate (circuit density). This in turn affects the cost of integrated circuits as well as the speed at which the circuits can operate and how much power is needed to operate the integrated devices.
Current efforts are being made to increase the resolution to below the micrometer level, more specifically, to the nanometer level. Advances, however, have been limited by the physics of light scatter and diffraction attributable to the wavelength of the light radiation used to expose the resist coated substrate through the mask. In this regard, the photolithographic masks are used in the far-field and conventional and commercial photolithographic techniques for manufacturing integrated circuits are Abbe-diffraction limited in their achievable resolution. This limits the size of features to be patterned on the substrate (namely, the semiconductor chips) to one-half the wavelength of the light used. Currently, the resolution is limited to a minimum dimension of about 0.2 micrometers. Attempts to move to shorter wavelengths of light have not shown much success. See, e.g., "The limits of lithography" Scientific American (September 1995), p. 66; and Stix, "Toward `point one`" Scientific American (February 1995), pp. 90-5.
Due at least in part to the difficulties in improving resolution in photolithography, there also has been considerable activity using alternate techniques for forming masks and patterns in substrates for semiconductor processing. These include electromagnetic radiation in the x-ray region and electron beams. Although these technologies have met with some technical success, they involve other considerations, in particular time and cost, in their implementation that have inhibited widespread adoption of the technology, and, to date, prevented implementing forming masks and patterns with sub-micrometer resolution in mass production. The term "nanoscale" as used herein means a dimensional resolution of a pattern or a structure that is sub-micrometer, more preferably less than 0.2 micrometers in resolution.
There also exists a device known as a scanning probe microscope in which a high-precision actuator moves a miniature sensor over the surface of a sample. See, for example, Jefferson, "The imaging of individual atoms", Science, V. 274 (Oct. 18, 1996), p. 369. Because the sensor and the sample interact only over a very small area, the scanning probe microscope attains a high resolution that can image nanoscale structures. Among the many types of scanning probe microscopes which have been built are scanning tunneling microscopes ("STM"), atomic force microscopes, scanning electrochemical microscopes ("SECM") and scanning near-field optical microscopes. See, generally, Dror, Scanning Force Microscopy: With Applications to Electric. Magnetic, and Atomic Forces, Oxford University Press, (New York, 1991).
A scanning tunneling microscope (STM) senses quantum tunneling of electrons. Electrons tunnel between an atomically sharp wire tip and an electrically conducting sample. A piezoelectric ("piezo") transducer scans the tip across the surface of the sample in a raster pattern. In one implementation, the resulting changes in tunneling current are recorded. However, it is more common to use a negative feedback loop to vary the height of the tip in response to minute changes in the tunneling current. This keeps the tip's height above the sample, and the tunneling current, constant. The output of the feedback loop also gives a measure of the height of the sample's surface. This is described in Binnig et al., "Surface studies by scanning tunneling microscopy" Physical Review Letters, V. 49 (Jul. 5, 1982), pp. 57-61.
The tunneling current falls off exponentially as the distance between the tip and the sample increases. It has been demonstrated that, typically, the tunneling current decreases by about an order of magnitude for each additional Angstrom of separation between the sample and the tip. Guntherodt et al. (eds.), Scanning Tunneling Microscopy I, (Springer-Verlag, New York, 1992) ("Guntherodt"). This leads to the extremely high resolution of an STM.
STM theory is treated more fully in the published literature. See, e.g., Guntherodt; Volodin, "Tactile microscopes" Quantum, V. 3 (January/February 1993) pp. 37-40; Binnig et al., "Vacuum tunneling" Physica, 109 & 110B (1982) pp. 2075-2077; Binnig et al., "Surface studies by scanning tunneling microscopy" Physical Review Letters, V. 49 (Jul. 5 1982) pp. 57-61; and Dror, Scanning Force Microscopy: With Applications to Electric, Magnetic, and Atomic Forces (Oxford University Press, New York, 1991). The reader is referred to each of the foregoing references for further details on STM design theory and applications.
One proposal to solve the problem of increasing the feature density on silicon wafers is the use of scanning tunnelling microscopes ("STMs") and atomic force microscopes (AFMs) to pattern the surface directly. See, for example, Zhang et al., "Creation of nanocrystals through a solid-solid phase transition induced by an STM tip," Science, V. 274 (Nov. 1 1996), pp. 757-60; and "Atomic landscapes beckon chip makers and chemists," Report from the American Vacuum Society Meeting, Science, V. 274 (Nov. 1 1996, pp. 723) (the "AVS Report"). It has been shown that these microscopes can manipulate individual atoms to create nanoscale structures. Unfortunately, these microscopes are too slow to create the millions of integrated circuit chips, each with millions of transistors, required by the semiconductor industry. Attempts to create AFMs with multiple tips working in parallel have shown only limited success, as noted in the aforementioned AVS Report.